1 document # sram102 rev a revised october 2005 features universal 256 x 4 static ram one part, the p93u422, replaces the following bipolar and cmos parts: ? 93422, 93422a ? 93l422, 93l422a fast access time ? 35 ns commercial and military available in the following packages: ? pdip, cerdip, side brazed dip ? cerpack ? lcc ? soic description the p93u422 is a 1,024-bit high-speed static ram with a 256 x 4 organization. the p93u422 is a universal device designed to replace the entire 93 and 93l 256 x 4 static ram families. the memory requires no clocks or refreshing and has equal access and cycle times. inputs and outputs are fully ttl compatible. operation is from a single 5 volt supply. easy memory expansion is provided by an active low chip select one ( cs 1 ) and p93u422 high speed 256 x 4 static cmos ram functional block diagram pin configurations cmos for low power ? 440 mw (commercial) ? 495 mw (military) 5v power supply 10% for both commercial and military temperature ranges separate i/o fully static operation with equal access and cycle times resistant to single event upset and latchup due to advanced process and design improvements active high chip select two (cs 2 ) as well as 3-state outputs. in addition to high performance, the device features latch- up protection, single event and upset protection. the p93u422 is offered in several packages: 22-pin 400 mil dip (plastic and ceramic), 24-pin 300 mil soic, 24-pin square lcc and 24-pin cerpack. devices are offered in both commercial and military temperature ranges. soic (s4) cerpack (f3) dip (p3-1, c3-1, d3-1) lcc (l4)
p93u422 page 2 of 10 document # sram102 rev a t a = 125c t a = 0c symbol v oh v ol v ih v il i il i ih i sc parameter output high voltage output low voltage input high level input low level input low current input high current output short circuit current (3) test conditions v cc = min., v in = v ih or v il , i oh = ?5.2 ma v cc = min., v in = v ih or v il , i ol = 8.0 ma v in = 0.40 v v cc = max, v in = 4.5v v cc = max., v out = 0.0v i cex output leakage current v cl input clamp voltage i in = ?10ma v out = 2.4v, v cc = max. t a = 75c t a = ?55c p93u422 min. 2.4 2.1 max. 0.45 0.8 ?300 40 ?70 70 70 80 90 ?1.5 unit v v v v a a ma ma v power supply current ?50 50 a all inputs = gnd v cc = max. i cc v out = 0.5v, v cc = max. maximum ratings (1) symbol parameter value unit v cc power supply pin with ? 0.5 to +7 v respect to gnd terminal voltage with ? 0.5 to v term respect to gnd v cc +0.5 v (up to 7.0v) t a operating temperature ? 55 to +125 c notes: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to maximum rating conditions for extended periods may affect reliability symbol parameter conditions typ. unit c in input capacitance v in = 0v 5 pf c out output capacitance v out = 0v 7 pf capacitances (4) (v cc = 5.0v, t a = 25c, f = 1.0mhz) recommended operating conditions symbol parameter value unit t bias temperature under ? 55 to +125 c bias t stg storage temperature ? 65 to +150 c i out dc output current 20 ma 2. extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. for test purposes, not more than one output at a time should be shorted. short circuit test duration should not exceed 30 seconds. 4. this parameter is sampled and not 100% tested. grade (2) commercial military ambient temp 0c to 70c ?55c to 125c gnd 0v vcc 5.0v 10% 5.0v 10% 0v dc electrical characteristics over recommended operating temperature and supply voltage (2)
p93u422 page 3 of 10 document # sram102 rev a mode cs 2 cs cs cs cs cs 1 we we we we we oe oe oe oe oe output standby l x x x high z standby x h x x high z d out disabled h l x h high z read h l h l d out write h l l x high z t s (di) t plz ( we ) (8) t phz ( we ) (8) truth table recovery times by eliminating the ?write recovery glitch.? reading is performed with chip selct one ( cs 1 ) low, chip select two (cs 2 ) high, write enable ( we ) high and output enable ( oe ) low. the information stored in the addressed word is read out on the noninverting outputs (o 0 through o 3 ). the outputs of the memory go to an inactive high impedance state whenever chip select one ( cs 1 ) is high, or during the write operation when write enable ( we ) is low. an active low write enable ( we ) controls the writing/ reading operation of the memory. when chip select one ( cs 1 ) and write enable ( we ) are low and chip select two (cs 2 ) is high, the information on data inputs (d 0 through d 3 ) is written into the addressed memory word and preconditions the output circuitry so that true data is present at the outputs when the write cycle is complete. this preconditioning operation insures minimum write functional description switching characteristics (5,6) over operating range (commercial and military) notes: h = high l = low x = don't care high z = implies outputs are disabled or off. this condition is defined as high impedance state for the p93u422. unit ns parameters t plh(a) (7) t plh(a) (7) t pzh ( cs 1, cs 2 ) (8) t pzl ( cs 1, cs 2 ) (8) t pzh ( we ) (8) t pzl ( we ) (8) t pzh ( oe ) (8) t pzl ( oe ) (8) t s (a) t h (di) t s ( cs 1, cs 2 ) t h ( cs 1, cs 2 ) t pw ( we ) t phz ( cs 1, cs 2 ) (8) t plz ( cs 1, cs 2 ) (8) t phz ( oe ) (8) t plz ( oe ) (8) description delay from address to output (address access time) (see fig. 2) delay from chip select to active output and correct data (see fig. 2) delay from write enable to active output and correct data (write recovery) (see fig. 1) delay from output enable to active output and correct data (see fig. 2) setup time address (prior to initiation of write) (see fig. 1) hold time address (after termination of write) (see fig. 1) setup time data input (prior to initiation of write) (see fig. 1) hold time data input (after termination of write) (see fig. 1) setup time chip select (prior to initiation of write) (see fig. 1) hold time chip select (after termination of write) (see fig. 1) minimum write enable pulse width (to insure write) (see fig. 1) delay from chip select to inactive output (high z) (see fig. 2) delay from write enable to inactive output (high z) (see fig. 1) delay from output enable to inactive output (high z) (see fig. 2) p93u422 5 5 5 5 5 5 20 max. min. 35 25 25 25 30 30 30 ns ns ns ns ns ns ns ns ns ns ns ns ns t h (a)
p93u422 page 4 of 10 document # sram102 rev a switching test test circuits (7, 8) notes: 5) test conditions assume signal transition times of 10 ns or less. 6) extended temperature operation guaranteed with 400 linear feet per minute of air flow. 7) t plh (a) and t phl (a) are tested with s 1 closed and c l = 15 pf with both input and output timing referenced to 1.5v 8) t pzh ( we ), t pzh ( cs 1 , cs 2 ) and t pzh ( oe ) are measured with s 1 open, c l = 15 pf and with both the input and output timing referenced to 1.5v. t pzl ( we ), t pzl ( cs 1 , cs 2 ) and t pzl ( oe ) are measured with s 1 closed, c l = 15pf and with both the input and output timing referenced to 1.5v. t phz ( we ), t phz ( cs 1 , cs 2 ) and t phz ( oe ) are measured with s 1 open, c l < 5pf and are measured between the 1.5v level on the input to the v oh -500mv level on the output. t plz ( we ), t plz ( cs 1 , cs 2 ) and t plz ( oe ) are measured with s 1 closed, c l < 5pf and are measured between the 1.5v level on the input to the v ol +500mv level on the output.
p93u422 page 5 of 10 document # sram102 rev a switching waveforms write mode (with oe = low) read mode key to diagram figure 1. figure 2.
p93u422 page 6 of 10 document # sram102 rev a selection guide the p93u422 is available in the following temperature range, speed, and package options. ordering information *military temperature range with mil-std-883, class b processing. speed (ns) 35 plastic dip -35pc plastic soic -35sc side brazed dip -35cm cerdip -35dm cerpack -35fm lcc -35lm side brazed dip -35cmb cerdip -35dmb cerpack -35fmb lcc -35lmb military processed* military temperature temperature range package commercial temperature
p93u422 page 7 of 10 document # sram102 rev a side brazed dual in-line package cerdip dual in-line package pkg # # pins symbol min max a - 0.200 b 0.014 0.026 b2 0.035 0.060 c 0.008 0.015 d - 1.100 e 0.360 0.410 ea e l 0.125 0.200 q 0.015 0.060 s1 0.005 - s2 0.005 - 0.100 bsc c3-1 22 (400 mil) 0.400 bsc pkg # # pins symbol min max a - 0.225 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.111 e 0.350 0.410 ea e l 0.125 0.200 q 0.015 0.070 s1 0.005 - 0 15 0.100 bsc d3-1 22 (400 mil) 0.400 bsc
p93u422 page 8 of 10 document # sram102 rev a square leadless chip carrier cerpack ceramic flat package pkg # # pins symbol min max a 0.060 0.090 b 0.015 0.022 c 0.004 0.009 d-0.630 e 0.330 0.380 e k 0.008 0.015 l 0.250 0.370 q 0.026 0.045 s-0.085 s1 0.005 - f3 24 0.050 bsc pkg # # pins symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d/e 0.395 0.410 d1/e1 d2/e2 d3/e3 - 0.410 e h j l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.095 nd ne 0.050 bsc 6 0.040 ref 0.020 ref 6 l4 24 0.250 bsc 0.125 bsc
p93u422 page 9 of 10 document # sram102 rev a small outline ic plastic package plastic dual in-line package pkg # # pins symbol min max a - 0.210 a1 0.015 - b 0.014 0.022 b2 0.045 0.065 c 0.009 0.015 d 1.065 1.120 e1 0.330 0.390 e 0.390 0.425 e eb - 0.500 l 0.115 0.160 0 15 0.100 bsc p3-1 22 (400 mil) pkg # # pins symbol min max a 0.093 0.104 a1 0.004 0.012 b2 0.013 0.020 c 0.009 0.012 d 0.598 0.614 e e 0.291 0.299 h 0.394 0.419 h 0.010 0.029 l 0.016 0.050 0 8 s4 24 (300 mil) 0.050 bsc
p93u422 page 10 of 10 document # sram102 rev a revisions document number : sram102 document title : p93u422 high speed 256 x 4 static cmos ram rev. issue date orig. of change description of change orig 1997 dab new data sheet a oct-05 jdb change logo to pyramid
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